1. Field of the Invention
The present invention relates to a pattern data generation method, and more particularly, it relates to a method of generating interconnect layer pattern data by an automatic arrangement/interconnection tool. The present invention also relates to a program for causing a computer to generate pattern data.
2. Description of the Related Art
Recently, elements constituting a semiconductor device such as a memory and an integrated circuit have been miniaturized. Accordingly, in the step of transferring a design pattern onto a wafer, an insufficient process margin between adjacent patterns tends to increase process risk points (also referred to as hot spots) where a short circuit or breakage may occur.
The insufficient process margin results in, for example, an error in which a pattern is connected or disconnected at an unexpected point or an error in which a line width or space does not satisfy predetermined conditions.
For these points, at least one of a design rule parameter, a process proximity effect correction parameter and a semiconductor process parameter is repetitively optimized to create a design layout change guideline. There has been disclosed a technique to partly modify a design layout on the basis of the design layout changing guideline (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2005-181524, Jpn. Pat. Appln. KOKAI Publication No. 2005-181612).
For example, Jpn. Pat. Appln. KOKAI Publication No. 2005-181612 has disclosed a technique for modifying edges constituting a pattern to derive a pattern satisfying predetermined conditions. Further, “Automated hotspot fixing system applied for metal layers of 65 nm logic devices” (S. Kobayashi et al., Proc. SPIE Vol. 6283, 62830R1-62830R11) has disclosed a technique for specifying amounts of modifications of a line width and a space width on a design layout to modify a process risk point such that the process risk point may be removed from the design layout.
In connection with these techniques, with regards a processing aspect when a single modification guide or a plurality of modification guides are generated in extracting risk points using a process simulator, it is difficult to determine which guide is the best for use in a modification when all factor such as the design, device characteristics, mask data processing (MDP), optical proximity effect correction (OPC), resolution enhancement techniques (RET), a mask formation process, a wafer machining process, etc., are considered.
When a process risk point is modified in accordance with lithography simulation information alone, electric characteristics of an interconnection are significantly changed, which may deteriorate signal integrity. For example, if a critical path or pattern located in the vicinity thereof is modified to a great extent, electric characteristics of the critical path are changed. In such a case, layout designing and timing verification are redone, leading to a significant deterioration in turnaround time (TAT) of the designing of a semiconductor device.